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TDA7529
RF front-end for AM/FM DSP car-radio with IF sampling
Features

Fully integrated VCO for world tuning High performance PLL for fast RDS system I/Q mixer for FM IF 10.7MHz with image rejection and integrated LNA I/Q mixer for AM IF 10.7MHz up conversion with high dynamic range Integrated balun, Which allows saving of external mixer tank RF AGC, IF AGC, DAGC Low noise IF amplifier with switched wide dynamic AGC range IF switch for FM / AM / IBOC Electronic alignment for the preselection stages I2C/SPI controlled single 5v SUPPLY Alternative frequency control signals to DSP
LQFP64
Description
The front-end is a high performance tuner circuit for AM/FM - DSP car-radios with 10.7MHz IF sampling. It contains mixer and IF amplifiers for AM and FM, fully integrated VCO and PLL synthesizer on a single chip. Use of BiCMOS technology allows the implementation of several tuning functions and a minimum of external components.
Table 1.
Device summary
Part number TDA7529 TDA7529TR Package LQFP64 exposed pad (10x10x1.4) LQFP64 exposed pad (10x10x1.4) Packing Tray Tape and reel
March 2007
Rev 1
1/60
www.st.com 1
Contents
TDA7529
Contents
1 2 3 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 IMR Mixer and active balun output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 FM RF-AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AM RF-AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IF AGC and IF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 D/A Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 GPIO - general purpose IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . 16 AFSAMPLE/AFHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Serial BUS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 IF - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Phase frequency detector and charge pump . . . . . . . . . . . . . . . . . . . . . . 25 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 D/A-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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TDA7529
Contents
4.14 4.15 4.16 4.17
A/D-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 GPIO - general purpose IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . 27 AFSAMPLE / AFHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5
Tuning state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1 Tuning state machine modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 Mode 000: buffer (nil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Mode 001: preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Mode 010: search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Mode 011: AF update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Mode 100: jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 5.3 5.4 5.5 5.6
Mode 100: check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Mode 110: load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Mode 111: end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Register SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 State machine start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6
Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 6.1.15 6.1.16 Short_reg (0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ADCctrl (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 GPIO mode (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AGC and mixer control (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Register (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Divider R (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 IF AGC control (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FM AGC (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AGC voltage threshold (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Mixer alignment 1 (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Mixer alignment 2 (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PLL control 1 (11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PLL control 2 (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PLL test (13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Misc 2 (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 WAIT LOCK (15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Contents 6.1.17 6.1.18 6.1.19 6.1.20 6.1.21 6.1.22 6.1.23 6.1.24 6.1.25 6.1.26 6.1.27 6.1.28 6.1.29 6.1.30 6.1.31 6.1.32 6.1.33 6.1.34 6.1.35 6.1.36
TDA7529 AGC time constant settings (16 / 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 AMAGC control (17 / 33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 GPIO output level control (18 / 34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 IF control (19 / 35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 AF state machine wait time 1 (20 / 36) . . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL main divider (N-divider) 1 (21 / 37) . . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL main divider (N-divider) 2 (22 / 38) . . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL main divider (N-divider) 3 (23 / 39) . . . . . . . . . . . . . . . . . . . . . . . . . 51 PLL Divider ratio calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 VCO divider (V-divider) (24 / 40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Charge pump current (25 / 41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Tuning DAC 1 (26 / 42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Tuning DAC 2 (27 / 43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DAC output voltage = 600mV + DACval * 9mV . . . . . . . . . . . . . . . . . . . 53 Different controls (28 / 44) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Misc 3 (29 / 45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Analog test select (30 / 46) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 AD converter test (31 / 47) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Read 1 (48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Read 2 (49) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7 8 9
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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TDA7529
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 IF AGC and IF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Switching frequency as a function of the process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 GPIO - general purpose IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Supports data communication using the SPI and the I2C protocol . . . . . . . . . . . . . . . . . . . 17 I2C addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 IF - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Phase frequency detector and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 D/A-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 A/D-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 GPIO - general purpose IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AFSAMPLE / AFHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Values of the programmable wait times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Short_reg (0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ADCctrl (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 GPIO mode (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AGC and mixer control (3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Register (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Divider R (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 IF AGC control (6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FM AGC (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AGC voltage threshold (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Mixer alignment 1 (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Mixer alignment 2 (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PLL control 1 (11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PLL control 2 (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PLL test (13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Misc 2 (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 WAIT LOCK (15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 AGC time constant settings (16 / 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 AMAGC control (17 / 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 GPIO output level control (18 / 34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 IF control (19 / 35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 AF state machine wait time 1 (20 / 36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL main divider (N-divider) 1 (21 / 37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL main divider (N-divider) 2 (22 / 38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61.
TDA7529
PLL main divider (N-divider) 3 (23 / 39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PLL Divider ratio calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 VCO divider (V-divider) (24 / 40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Charge pump current (25 / 41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Tuning DAC 1 (26 / 42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Tuning DAC 2 (27 / 43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Different controls (28 / 44) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Misc 3 (29 / 45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Analog test select (30 / 46) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 AD converter test (31 / 47) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Read 1 (48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Read 2 (49) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6/60
TDA7529
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Positive current diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Positive/negative current diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Voltage and current mode with hand-over . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C (sub address mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Preset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Search timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AF update timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Jump timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Check timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Load timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 End timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Buffer/control serial bus sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LQFP64 (10x10x1.4mm) exposed pad down mechanical data and package dimensions (exposed pad size for D2 and E2: 4.5mm max.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7/60
Functional block diagram
TDA7529
1
Functional block diagram
Figure 1. Functional block diagram
IBOC
FM
DAGC
AM 2 IF 10.7MHz MSB/LSB
AGC
FM WX
2 2 I Q
AGC AFHOLD AFSAMPLE I2C SPI
AF update
AGC TV1 TV2
Bus Interface Supply
2 AM I Q DIV :N VCO
PLL
DIV 2 Fref
AC00038
8/60
TDA7529
Pins description
2
Pins description
Figure 2. Pin connection
Balunout2 Balunout1 VCCRF2 GNDRF2 BIASD1 TCAM VCCIF TCFM TCIF2
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 BALUN1 BALUNdec DAC2 DAC1 FMMIX1in FMMIX1dec FMAGC2/GP7 FMAGC1 FMMIX2in FMMIX2dec GNDRF1 AMAGC1 AMMIXdec AMMIXin MIXbiasdec IFAGC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GNDIF TCIF1 IFout1 IFout2 BIASD2 VDDdec VCCBUS MISO MOSI CLK CS/AS PS BUSGND VCCRO XTALO XTALI
VCCRF1
VCOdec1
Vtune
VCOdec2
GNDVCO
LFHC
GNDPLL
VCCPLL
IFdec GP1
IFin2
IFin2
IFin3
IFin4
GP5
GP2
GP4/VDS
AMAGC2/GP8
AFSAMPLE
AFHOLD
GNDRO
IFAG2
LFLC
AC00039
Table 2.
Pin # 1 2 3 4 5 6 7 8 9
Pin assignment
Pin Name BALUN1 BALUNdec DAC2 DAC1 FMMIX1in FMMIX1dec active balun input 1 active balun input 2 (de coupling) Tuning DAC 2 output Tuning DAC 1 output FM mixer input - high gain stage = mode 1 FM mixer de couple Description
FMAGC2/GP7 FM AGC voltage output / alternative GP7 output FMAGC1 FMMIX2in FM PIN diode driver output FM Mixer input - low gain stage = mode2
9/60
Pins description Table 2.
Pin # 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
TDA7529 Pin assignment (continued)
Pin Name FMMIX2dec GNDRF1 AMAGC1 AMMIXdec AMMIXin MIXbiasdec IFAGC1 IFAGC2 GP4/VDS AMAGC2 / GP8 AFHOLD AFSAMPLE VCCRF1 VCOdec1 Vtune VCOdec2 GNDVCO LFLC LFHC GNDPLL VCCPLL GP1 GNDRO XTALI XTALO VCCRO BUSGND PS CS/AS CLK MOSI MISO VCCBUS VDDdec FM Mixer de couple GND RF1 section AMAGC PIN diode driver output AM mixer de couple AM mixer input Mixer bias de coupling IFAMP gain control via IFAGC - LSB IFAMP gain control via IFAGC - MSB GPIO 4 / VDS input AMAGC voltage output / alternative GP8 output AF state machine hold output AF state machine sample output Supply RF1 section BIAS de couple for VCO VCO tuning voltage BIAS de couple for VCO VCO Ground Loop filter low current output Loop filter high current output PLL Ground Supply PLL GPIO 1 Ground PLL digital part Reference oscillator input Reference oscillator output Supply PLL digital part BUSinterface Ground Protocol Select Chip select / Address select SPI / I2C clodk SPIdata input / I2C Data SPI Data Output Supply of BUSinterface De couple of internal 3.3V (=3,3V + Vbe) Description
10/60
TDA7529 Table 2.
Pin # 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Pins description Pin assignment (continued)
Pin Name BIASD2 IFout2 IFout1 TCIF1 GNDIF TCIF2 IFdec IFin4 VCCIF IFin3 BIASD1 IFin2 GP2 IFin1 GP5 GNDRF2 TCAM TCFM VCCRF2 Balunout1 Balunout2 De coupling for Biasing Differential IF output 2 Differential IF output 1 time constant IF AGC for AM ground IF section time constant IF AGC for FM De couple of IF amplifier IF input 4 Supply IF section IF input 3 De coupling for Biasing IF input 2 GPIO 2 IF input 1 GPIO 5 GND RF2 section = active balun GND AM AGC time constant FM AGC time constant Supply voltage RF2 section Active balun output 2 = FM output Active balun output 1 = AM output Description
11/60
Function description
TDA7529
3
3.1
Function description
IMR Mixer and active balun output
The IMR mixer has two FM inputs (referred as mode 1 / mode 2) and one AM input selectable by software. The FM inputs differ by their gains, noise figures, IIP3 and maximum signal handling capability. The mode 1 FM input (with the higher gain, lower IIP3 and lower noise figure) is normally coupled with passive antenna input stages; the mode 2 FM input is normally used for input stages featuring an external preamplifier. There are two single ended outputs of the IMR mixer: Balunout1 has a 4 dB higher gain than Balunout2. It is not recommended to use both outputs in parallel. The Balun1 pin is the current mixer output over an internal resistor. The LC filter at Balun1 can be realized with a low cost SMD-coil (Q ~ 4).
3.2
FM RF-AGC
The FM AGC system is controlled by a peak detector, whose gain can be varied by the keyed AGC. The latter function is meant to be controlled by a D/A converter in the back-end part of the system. The time constant of the FM RF-AGC is defined by an external capacitor connected to TCFM and programmable internal currents. The currents can be selected independently for AGC attack and decay. By this the ratio between the attack and the decay time can be programmed between 0.4 and 250. The FM RF-AGC has two output pins to drive one PIN diode attenuator and the external preamplifier gain control. The AGC outputs can be programmed to the following modes: 1. Positive current I=f(e): after reaching the AGC threshold voltage, the current output delivers a current I=f(e) up to 15mA in a voltage range from 0.1V (@10A sink current) up to VCC-1.2V with a quasi-exponential characteristic referred to the voltage at TCFM. Positive current diagram
Iout
Figure 3.
15mA
f(e) current
V_TCFM
AC00040
2.
Pos/neg current I = f(e): below the AGC threshold voltage the AGC output sinks a constant current of -5 mA. When the RF input level crosses the AGC threshold voltage, the current is reduced down to 0 mA with a quasi-logarithmic behavior. At half control voltage the current becomes positive and reaches up to 15mA following an exponential function.
12/60
TDA7529 Figure 4. Positive/negative current diagram
Iout
Function description
15mA
f(e) current 1.65V
AC00041
3. 4.
Constant current mode: the output current can be set to 2 mA source current. The AGC detector is in power -down mode and only the PIN diode driver is active. Voltage and current mode with hand-over: the Vthr level is programmable with 6 bit in the range of 0.2V to 2.56V. The voltage Vthr is the internal reference voltage of an external cascode transistor emitter feedback loop. Voltage and current mode with hand-over
Iout Vout
Figure 5.
Vthr
Vthr
AC00042
The voltage output swing is comprised between 0V and 3.3V (VDD). The microcontroller can read the voltage at the AGC capacitor via the serial control interface.
3.3
AM RF-AGC
The AM AGC system is controlled by an average detector. The time constant of the AM RFAGC is defined by an external capacitor connected to TCAM and programmable internal currents with symmetrical attack/decay behavior. The AM RF-AGC has two output pins to drive one PIN diode attenuator and the external preamplifier gain control. The AGC outputs can be programmed to the same modes as the FM RF-AGC with the exception of pos/neg current. The microcontroller can read the voltage at the AGC capacitor via the serial control interface.
13/60
Function description
TDA7529
3.4
IF AGC and IF amplifier
The IF AGC system is controlled in AM with an average detector and in FM with a peak detector, and reduces the mixer gain. The time constant is defined by two external capacitors connected to TCIF1 and TCIF2 respectively, and programmable internal currents. The microcontroller can read the voltage at the AGC capacitors via the serial control interface. The IF amplifier gain is not affected by the on-chip IF-AGC but is meant to be controlled by the back-end part of the system through pins IFAGC1 and IFAGC2. The gain is reduced in 6 dB steps starting from the programmed value "G" according to the following table: Table 3. IF AGC and IF amplifier
IFAGC2 0 0 1 1 IFAGC1 0 1 1 0 Gain G G - 6dB G - 12dB G - 18dB
3.5
Dividers
The mixer divider V is followed by a divide-by-4-stage that generates 0/90/-90 LO signals for the IMR mixer (90/-90 mode to switch between upper or lower side-band suppression in the IMR mixer). The main divider N can be operated in integer mode.
3.6
D/A Converters
The front-end contains two D/A-converters for tuning the filters of the FM pre-stage. The converters have a resolution of 9 bit.
14/60
TDA7529
Function description
3.7
VCO
The 3.7 GHz VCO has an internal switch that allows extending the oscillation frequency range. This is required by the fact that each of the two resulting VCO sub-bands (upper/lower) cannot individually cover the complete required frequency range versus temperature and process; for this reason a calibration procedure is needed to determine the process type (typical, slow, fast) and select the transition frequency between the two VCO sub-bands. To run the procedure the VCO range 2 must be selected, the synthesized frequency needs to be set to 4GHz; then if Vtuning > 2.6V then the process is 'slow', if Vtuning < 1.7V then is 'fast' and otherwise is 'typical'. The switching frequency as a function of the process is reported in the following table: Table 4. Switching frequency as a function of the process
SLOW 3.635GHz TYP 3.72GHz FAST 3.794GHz
3.8
FREF
The reference frequency for the PLL can be derived by a XTAL directly connected to the device or by means of an LVDS signal. In the latter case an external matching resistor must be used to obtain the desired input signal level.
3.9
A/D converter
The front-end contains a 6 bit SAR A/D-converter for sensing several analog values of the tuner. The following analog sources can be switched to the ADC input by software command:

FM RF AGC capacitor voltage AM RF AGC capacitor voltage IF AGC capacitor voltage (automatically connected to the FM or AM IF AGC filtering capacitor) PLL tuning voltage Temperature sensor GPIO 1 voltage GPIO 2 voltage ADC reference generated from VCC.
The ADC can be clocked by an integrated RC-oscillator, in which case the oscillation frequency is programmable, or by the PLL reference frequency.
15/60
Function description
TDA7529
3.10
GPIO - general purpose IO interface pins
The front-end has seven GPIO - general purpose control pins to switch external stages (output), e.g amplifiers, or to read the status of external stages (input), e.g. control voltages. Some control pins are multiplexed with other functions that are not necessary in every tuner design (FM AGC keying, AM cascode control). All the GPIOs may put in tristate or in enable mode. When in enable the GPIOs can be configured as shown in the following table. All GPIOs are short-circuit protected by current limiter and voltage-tolerant up to 3.5V. Table 5. GPIO - general purpose IO interface pins
FUNCTION selects function of GPIO1: if input, connects GPIO1 to ADC (ADC must then be configured - AnlgIn to AD to use GPIO1 as input); if output, level depends - DigOut on GPIO Out Lev Ctrl GPIO1 selects function of GPIO2: if input, connects GPIO2 to ADC (ADC must then be configured to use GPIO2 as input) and to KAGC (FM KAGC must then be enabled); if output, level depends on GPIO Out Lev Ctr GPIO2 selects function of GPIO4: if input, configures GPIO4 as AM Cascode VDS input; if output, level depends on GPIO Out Lev Ctrl GPIO4
GPIO ports
GPIO1
GPIO2
- AnlgIn to AD - Kagc In - DigOut
GPIO4
- AnlgIn - DigOut
GPIO5
selects function of GPIO5: if input, it is directly connected to read-only register byte 48 bit 4; if output, level depends on GPIO Out Lev Ctrl GPIO5. - DigIn When set to input, it is necessary to set IF AMP - Out (Dig or Anlg) GPIO5 out mode to "ON GPIO5 out En" (labels are wrong). Also used for production testing as analog output (not relevant for application). selects function of GPIO6 if device is configured in I2C mode: if input, it is directly connected to read-only register byte 48 bit 5; if output, level depends on GPIO Out Lev Ctrl GPIO5. When the device is configured in SPI mode, program GPIO Out Lev Ctr GPIO5 to "Low". The value of GPIO mode GPIO5 does not matter
GPIO6
- Din (spi MISO out) - Dout (spi MISO out)
GPIO7
selects function of GPIO7: if digital output is selected, level depends on GPIO Out Lev Ctrl - Digital Out GPIO7; otherwise, configures GPIO7 as FM - FM agc Vout AGC Vout selects function of GPIO8: if output, level depends on GPIO Out Lev Ctrl GPIO8; otherwise, configures GPIO8 as AM AGC Vout - Digital Out - AM agc Vout
GPIO8
16/60
TDA7529
Function description
3.11
AFSAMPLE/AFHOLD
On the TDA7529 there are two dedicated open drain pins (AFSAMPLE and AFHOLD), that allow the control of the DSP (mute and quality controls) during AF update. Details are given in Chapter 5.
3.12
Serial BUS interface
The TDA7529 has a serial data port for communication with the microcontroller. It is used for programming the device and for reading out its detectors. This port supports data communication using the SPI and the I2C protocol. The data transfer of several consecutive bytes is supported by the auto increment feature. Table 6. Supports data communication using the SPI and the I2C protocol
Pin Signal 1 Signal 2 Signal 3 Signal 4 Signal 5 PS CS CLK MOSI MISO SPI signal Protocol Select SPI/I2C Chip Select Clock Master Out - Slave In Master In - Slave Out Pin PS AS CLK DATA GP6 I2C signal Protocol Select SPI/I2C Address Select Clock bidirectional Data General Purpose Out
The "PS"- pin (Protocol Select) determines which communication protocol is used. The information is not latched, so any level change at this pin immediately affects the protocol used by the TDA7529. The SPI protocol is selected by setting PS = 0 while, during the I2C operation, PS needs to be open (internally set to 1). SPI-Protocol: CPOL=1, CPHA=1. The CS pin performs the Chip Select function during the SPI operation; it has to be reset to 0 during transmission or reception, otherwise set to 1 (the CS pin is set to 1 by leaving it open). Both the CS and the AS functions are performed by the CS pin. When the I2C mode is used, the "AS" pin determines which I2C address or group of addresses (see below) is used. Three different external connections are defined to represent three groups of addresses (refer to the following table for details). The information is not latched, so any level change at this pin immediately affects the address used by the TDA7529. First the IC address is transmitted including the R/W bit for setting the direction of the following data transfer
17/60
Function description Table 7. I2C addresses
Tuner: level at pin AS address: MSB ... LSB 1100 000d 1100 001d 1100 010d 1100 011d 1100 100d 1100 101d 1100 110d 1100 111d
x d R/W W
TDA7529
Tuner 3 2.2V - 3.5V 1100 1xxd
Tuner 2 1.1V - 1.7V 1100 x1xd
Tuner 1 0.0V - 0.6V 1100 xx1d
R/W R/W W R/W W W W W W W W W
= must be "0" for reading, can be "1" or "0" for writing to the TDA7529 = determinates the direction of data transfer, reading or writing = indicates the address to read to and/or to write from a single TDA7529 = indicates those addresses that can be used to transmit equal data to several TDA7529 frontends. A read out has no purpose for these addresses (data collision), but must be possible without damaging the tuner IC. 2
The two serial bus protocols, I C and SPI, are as follows: Figure 6.
7 address
I2C (sub address mode)
1st byte 1 0 R/W 7 SM 2nd byte 1 subaddress N 0 x 7 data byte N 3rd byte 0 7 data byte N+1 4th byte 0
AC00043
Figure 7.
7 SM
SPI
1st byte 1 subaddress N 0 R/W 7 data byte N 2nd byte 0 7 data byte N+1 3rd byte 0 7 data byte N+2 4th byte 0
AC00044
Data auto increment mode is always active regardless of the serial bus mode chosen.
18/60
TDA7529
Electrical specifications
4
Electrical specifications
Electrical parameters are guaranteed if Fref = 100kHz, with frequency stability of +/- 20ppm max.
4.1
Table 8.
Symbol VCC Tamb Tstg Tj
Absolute maximum ratings
Absolute maximum ratings
Parameter Abs. supply voltage Ambient temperature range Storage temperature Junction temperature -40 -55 Test Condition Min Typ Max 5.5 105 150 150 Units V C C C
4.2
Table 9.
Symbol
Thermal data
Thermal data
Parameter Test Condition, Comments Min Typ Max Units
Rthj-amb
2s2p std Jedec board with thermal via underneath the Thermal resistance junction to component (36 board via: ambient diameter = 0.5mm / pitch = 1.5mm), max 30% missing soldering
33
C/W
4.3
Table 10.
Symbol VCC ICC ICC_pwd Tamb
General key parameters
General key parameters
Parameter 5V supply voltage Supply current @ 5V Supply current @ 5V in power down mode Ambient temperature range -40 Test Condition, Comments Min 4.7 Typ 5 145 9 Max 5.35 175 14 105 Units V mA mA C
19/60
Electrical specifications
TDA7529
4.4
FM - section
Refer to application circuit in figure 3. VCC = 4.7V to 5.35V; Tamb = -40 to +105C; fc = 76 to 108 MHz; 60dBV antenna level; mono signal, unless otherwise specified. Antenna level equivalence: 0dBV = 1Vrms, all RF levels are intended as PD.
Table 11.
Symbol
FM - section
Parameter Test Condition, Comments Min Typ Max Units
FM IMR Mixer and active balun Gmix1 Mixer conversion gain Gain attenuation range Rin Rout Vout_max Input impedance Output impedance Max. output voltage mode 1 (unloaded) mode 2 (unloaded) controlled by IF-AGC mode 1 mode 2 active balun without clipping (unloaded) Mode1, Rsource=1.5k, noiseless Mode 2, Rsource=800, noiseless mode 1 up to Vin/tone = 90 dBV mode 2 up to Vin/tone = 98 dBV mode 1 mode 2 without gain/phase adjust with gain/phase adjust 123 132 144 152 30 40 45 20 14 18 30 5 15 122 3 5 125 dBV 134 dBV dB 3.7 nV/Hz 6 22 16 20 50 6.5 20 9.5 30 24 18 dB dB k dBV
vnoise
Input noise voltage
IIP3
3rd order intercept point(1)
IIP2 IRR FM RF AGC
2nd order intercept point Image rejection ratio
mode 1, min. setting Lthr Mixer input referred RF level threshold mode 1, max setting mode 2, min. setting mode 2, max setting Threshold steps Pin diode source current Pin diode sink current Pin diode source current in constant current mode Threshold shift keyed AGC
1. parameter guaranteed by correlation.
82 97 90 105 0.5 10
85 100 93 108 1
88 103 96 111 1.5 dB mA -3 mA mA 13.5 dB/V dBV
4 bit control AGC control pin 1 Logarithmic current AGC control pin 1 Logarithmic current
1 Control input = 1V 10.5
2 12.5
20/60
TDA7529
Electrical specifications
4.5
AM - section
Refer to application circuit in figure 3. VCC = 4.7V to 5.35V; Tamb = -40 to +105C; LW, MW and SW bands; 74dBV antenna level, unless otherwise specified. Antenna level equivalence: 0dBV = 1Vrms, all RF levels are intended as EMF.
Table 12.
Symbol
AM - section
Parameter Test Condition, Comments Min Typ Max Units
AM IMR Mixer and active balun Gmix1 gmix1 Rin Rout Mixer conversion gain Gain attenuation range Input impedance Output impedance Min. external load Vin_max Vnoise IIP3 IIP2 IRR IRR AM RF AGC External capacitance for time constant from 1nF to 4700nF - time constant values are directly proportional to the external capacitor value Lthr Mixer input referred RF level threshold threshold steps Pin diode source current Min. voltage Isink Pin diode source current in constant current mode Max. voltage Max. output voltage in GPO mode Min. output voltage AGC control pin 1 AGC control pin 2 AGC control pin 2 min. setting max setting 4 bit control AGC control pin 1 Logarithmic current AGC control pin 1 with 5A sink current 5A sink current 5 1 VCC1.4 VDD0.3 VCC-1.2 VDD 0.3 10 83 98 0.5 10 0.1 86 101 1 89 dBV 104 1.5 dB mA V A mA V V V Max. output voltage Input noise voltage 3 order intercept point 2nd order intercept point without gain/phase adjust with gain/phase adjust
rd
7.2 controlled by IF-AGC 18 5 15 400 without clipping (unloaded) 122
9 20 6.5 20
10.5
dB dB
9.5 30
k W W dBV
6 130 159 30 40 45 134
8.3
nV/Hz dBV dBV dB dB
Image rejection ratio Image rejection ratio
21/60
Electrical specifications Table 12.
Symbol
TDA7529
AM - section (continued)
Parameter Fast attack time constant Test Condition, Comments active in case of overdrive (more than 7dB) Range, mode T1 Range, mode T2 Range, mode T3 Min 0.05 Typ 0.5 0.5-50 2.5-250 12.51250 Max 5 Units ms ms ms ms
Time constant
4.6
Table 13.
Symbol
IF - section
IF - section
Parameter Test Condition, Comments Min Typ Max Units
IF AMPLIFIER Input 1-3 (FM,HD,AM), min. Input 1-3 (FM,HD,AM), max Grange Gain range Input 4 (HD-Radio AM), min. Input 4 (HD-Radio AM), max Gstep AGC Rin_input1 Rin_input2 Rin_input3 Rin_input4 Rout Vout_max Gain, load Gain step AGC range AGC steps Input impedance input 1 Input impedance input 2 Input impedance input 3 Input impedance input 4 Differential output impedance Max. output voltage Gain variation in loaded conditions IIP3 decrease in loaded conditions 3rd order intercept point 10pF between each IFAMP outputs and GND, 10k differential load 10pF between each IFAMP outputs and GND, 10k differential load input stage 1-3, @ 25dB gain input stage 4, @ 17dB gain IIP2 2nd order intercept point input stage 1-3 input stage 4 119 130 142 dBV 154 122 dBV 133 115 2-bit control FM -input @ 10.7MHz HD-Radio FM input @ 10.7MHz AM input @ 10.7MHz HD-Radio AM input @ 10.7MHz 3 bit control 15 29 1.5 16.5 5.2 230 2.2 7 7 17 31 2 18 6 330 2.9 8.2 8.7 15 117 0.5 19 33 2.5 19 6.6 450 3.6 10 11 W k k k W dBV dB dB dB 23 36 25 38 27 40 dB
IIP3,load
1
dB
IIP3
22/60
TDA7529 Table 13.
Symbol
Electrical specifications IF - section (continued)
Parameter Test Condition, Comments @ source impedance 330 * noiseless, @31dB gain @ source impedance 470 * noiseless, @ 31dB gain, with external 560 input termination resistor @ source impedance 2.2k * noiseless, @ 29dB gain, with external 2.7k input termination resistor @ source impedance 2.2k * noiseless, @ 24dB gain, with external 2.7k input termination resistor Min Typ 3.5 Max 4.2 Units nV/Hz
Vnoise_input 1 IN1 input noise voltage
Vnoise_input 2 IN2 input noise voltage
3.8
4.6
nV/Hz
Vnoise_input 3 IN3 input noise voltage
5
6.5
nV/Hz
Vnoise_input 4 IN4 input noise voltage
7
8.5
nV/Hz
IF AGC External capacitance for time constant from 10nF to 500nF in FM (asym. mode), from 100nF to 4700nF in AM (sym. mode) - time constant values are directly proportional to the external capacitor value FM, min. setting FM, max setting Lthr IFAmp input referred AM, min. setting AM, max setting Threshold steps Fast attack mode in AMmode, range active in case of overdrive FM: asym. mode U1 FM: asym. mode U2 AM: sym. mode S1 AM: sym. mode S2 FM: asym. mode U1 / U2 AM: sym. mode S1 AM: sym. mode S2 86.5 96.5 1 0.05 89 99 1.5 0.5 10-500 0.05-2.5 2.0-100 20-1000 2-100 2-100 20-1000 91.5 101.5 2 5 dB ms s ms ms ms ms ms ms 88.5 99.5 91 101 93.5 103.5 dBV
Time constant attack, range
Time constant decay, range
23/60
Electrical specifications
TDA7529
4.7
Table 14.
Symbol
VCO
VCO
Parameter Frequency range VCO Test Condition, Comments 8% tuning range Free running VCO; values referred @ 100MHz @ 10 Hz @ 100 Hz @ 1 kHz @ 10 kHz FM reception, de-emphasis 50s, fNF=20Hz...20kHz @ min. VCO frequency Min 3430 Typ Max 4010 Units MHz
Phase Noise of LO
-46 -76 -103
-40 -60 -86 -106 8
dBc/Hz
Deviation error
Hz
4.8
Table 15.
Symbol
Reference frequency input buffer
Reference frequency input buffer
Parameter Test Condition, Comments Min Typ Max Units
Reference frequency input buffer mode Max input voltage high Min. input voltage low Input differential voltage Input impedance (xtal mode) Input impedance (lvds mode) Input voltage range Single ended mode 925 200 150 10 200 1000 400 1475 mV mV mV k k mVPP
4.9
Table 16.
Symbol
Dividers
Dividers
Parameter Test Condition, Comments Min Typ Max Units
Mixer divider V - integer values NV divider value divider_V 7 bit 5 131
Divide by 4 - generation of 0/90/-90 LO signal for IMR I/Q phase error of divider Main divider N - integer divider NN divider value divider_N 21bit (32/33 pre scaler) 992 2097151 phase calibration in IMR -0.5 0.5 DEG
Reference divider R - integer values NR divider value divider_R 8 bit 1 255
24/60
TDA7529
Electrical specifications
4.10
Table 17.
Symbol
Phase locked loop
Phase Locked Loop
Parameter Settling time AM/FM Spurious suppression Test Condition, Comments f < 0,01% @ fPFD = 100 kHz @ divided VCO signal 70 Min Typ 800 Max 1200 Units s dB
4.11
Table 18.
Symbol PFD fPFD
Phase frequency detector and charge pump
Phase frequency detector and charge pump
Parameter Test Condition, Comments Min Typ Max Units
PFD input frequency
2
3000
kHz
Charge pump high current mode bit1 high current mode bit2 high current mode bit3 high current mode bit4 low current mode bit5 low current mode bit6 low current mode bit7 low current mode bit8 low current mode bit9 high current mode bit1 high current mode bit2 high current mode bit3 high current mode bit4 low current mode bit5 low current mode bit6 low current mode bit7 low current mode bit8 low current mode bit9 -0.4 -0.8 -1.7 -3.1 -40 -80 -160 -320 -640 0.4 0.8 1.7 3.1 40 80 160 320 640 -0.65 -1.3 -2.4 -4.5 -60 -120 -240 -480 -960 0.65 1.3 2.4 4.5 60 120 240 480 960 -0.9 -1.7 -3.1 -5.8 -80 -160 -320 -640 -1280 0.9 1.7 3.1 5.8 80 160 320 640 1280 mA mA mA mA A A A A A mA mA mA mA A A A A A
Sink current
Source current
25/60
Electrical specifications
TDA7529
4.12
Table 19.
Symbol
Temperature sensor
Temperature sensor
Parameter Temperature range Resolution Absolute error Relative error 0.5 C/LSB (no direct measurement possible) Test Condition, Comments Min -40 5 15 Typ Max 150 Units C C C LSB
4.13
Table 20.
Symbol
D/A-Converter
D/A-Converter
Parameter Test Condition, Comments Min 0.5 VCC - 0.2 Typ 0.6 VCC - 0.1 2 500 resolution 9bit 8.5 -2 -0.5 @ CL=1nF 20 20 9 9.5 2 0.5 40 Max 0.8 Units V V k A mV LSB LSB s dB
Output voltage minimum value Unloaded output Vout Output voltage maximum value Output impedance Max. output current Average Voltage step INL DNL Conversion time VSRR Supply voltage ripple rejection ratio Unloaded output
4.14
Table 21.
Symbol
A/D-Converter
A/D-Converter
Parameter INL DNL Input voltage range Test Condition, Comments Min -2 -0.5 0 Typ Max 2 0.5 VDD 7 Units LSB LSB V s
tADC
Conversion time
26/60
TDA7529
Electrical specifications
4.15
Table 22.
GPIO - general purpose IO interface pins
GPIO - general purpose IO interface pins
GPIO functionality GPIO-Output GPIO-Input Multiplexed functionality details are given in the corresponding chapters
Pin name
High level voltage
Low level Functionality voltage
Source Sink voltage current current 1 mA 1 mA 0.1 mA 1 mA 1 mA 1 mA 1 mA 0V 0V 0V 0V 0V 0V 0V 1 mA 1 mA 1 mA 1 mA 1 mA 1 mA
GP1 GP2 GP4 GP5 GP6 GP7 GP8 Symbol
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
Analog input ADC Analog input ADC Digital Input Digital Input
0 ... 3.3V 0 ... 3.3V FM key AGC input 0 ... 3.3V 0 / 3.3V 0 / 3.3V SPI MISO output FM-AGC voltage output AM-AGC voltage output
10 mA AM cascode VDS input
Parameter High level output voltage Low level output voltage High level source current High level source current low level sink current low level sink current Input impedance Input voltage range High level input voltage Low level input voltage
Test Condition @ 100k load to GND @ 100k load to VDD GP1 / GP2 / GP5 / GP6: @ 1k load to GND GP4 @ 1k load to GND GP1 / GP2 / GP5 / GP6: @ 1k load to VDD GP4: @ 100 load to VDD digital input mode GP1 / GP2 GP5 / GP6 used as digital input GP5 / GP6 used as digital input
Min VDD-0.3
Typ
Max
Units V
0.3 0.5 0.08 1 0.1
V mA mA
0.8 8.0 100 0 2.2 -0.05
1 10 3.5 3.5 1.0
mA mA k V V V
4.16
Table 23.
Symbol
AFSAMPLE / AFHOLD
AFSAMPLE / AFHOLD
Parameter Output voltage at AFSAMPLE/AFHOLD Maximum sink current Vo = 0.4V 800 Test Condition, Comments Min Typ Max 3.6 Units V A
27/60
Electrical specifications
TDA7529
4.17
Table 24.
Symbol VDD fclk
Serial Data Interface
Serial Data Interface
Parameter Supply voltage Clock frequency Power On Delay time High level output voltage Low level output voltage High level source current low level sink current Rise / fall time High level input voltage Low level input voltage High level input voltage Guaranteed range @ SPI Guaranteed range @ I2C Ready for communication after Power-On-Reset Output signals Output signals Output signals Output signals Output signals, 90% Input signals, except AS Input signals, except AS AS input signal VDD-0.3 -0.05 0.08 0.8 15 2.0 -0.05 2.2 1.1 -0.05 100 100 0.01 1000 0.1 1 25 40 3.5 1.0 3.5 1.7 0.6 Test Condition, Comments Min 2.7 4 1 10 VDD 0.3 Typ Max 3.5 Units V MHz MHz ms V V mA mA ns V V V V V k k s
Medium level input voltage AS input signal Low level input voltage Input impedance Power-On impedance AS input signal Input signals All signals Input signals except CLK, min. acceptable duration range, 90% Rise / fall time Input signal CLK, min. acceptable duration range, 90%
0.01
10
s
28/60
TDA7529
Tuning state machine
5
Tuning state machine
Frequency changes in a system employing the TDA7529 can be efficiently performed using a built-in state machine which simplifies the microprocessor supervisory functions. The state machine, which can work in 8 different modes, can be invoked by a simple WRITE operation into the tuner registers and, provided that the frequency to be jumped to has been preloaded into the front-end registers through a previous separate or is loaded through a concurrent WRITE operation, the FE jump sequence is automatically managed and flags are provided to the back-end to indicate the current condition.
5.1
Tuning state machine modes
Hereafter the description of the 8 modes can be found. They are chosen by Byte 12 bits<6:4>. The diagrams depicting the FE and flag conditions for each of the 8 modes are as follows:
5.1.1
Mode 000: buffer (nil)
When this mode is selected, no action is undertaken by the state machine.
5.1.2
Mode 001: preset
Figure 8.
EVENTS
Preset timing diagram
bus STOP event regs swap
TIME
transmission with subaddr. bit 7 = 1
wait T1ms
wait for Tplllock
wait 50 us
wait T60ms
AFSAMPLE
AFHOLD
B.E. OPERATION
mute audio
quality dets in fast mode
unmute audio
AC00045
This mode is used to jump to a different frequency and stay there, with reception at the end of the sequence. AFSAMPLE can be used to tell the back-end when to mute and to unmute the audio output. The 60 ms mute time (programmable) after the PLL has reached the locked condition can be used to check the RDS signal presence and content in addition to the analog quality information. AFHOLD can be used to tell the back-end to switch to faster time constants for quick quality acquisition.
29/60
Tuning state machine
TDA7529
5.1.3
Mode 010: search
Figure 9.
EVENTS
Search timing diagram
bus STOP event regs swap
TIME
transmission with subaddr. bit 7 = 1
wait T1ms
wait for Tplllock
wait 50 us
AFSAMPLE
AFHOLD
B.E. OPERATION
mute audio
quality dets in fast mode
AC00046
This mode is used to jump to a different frequency and stay there, with audio muted. AFSAMPLE can be used to tell the back-end when to mute the audio output. AFHOLD can be used to tell the back-end to switch to faster time constants for quick quality acquisition.
5.1.4
Mode 011: AF update
Figure 10. AF update timing diagram
EVENTS bus STOP event regs swap regs swap
TIME
transmission with subaddr. bit 7 = 1
AFSAMPLE
AFHOLD
B.E. OPERATION
mute audio
hold
unmute audio
freeze AF qual
AC00047
This mode is used to jump to an AF frequency, check its quality, jump back to the starting frequency and continue reception. AFSAMPLE can be used to tell the back-end when to acquire the AF frequency quality. AFHOLD can be used to tell the back-end to mute/unmute the audio and keep normal processing on hold.
30/60
TDA7529
Tuning state machine
5.1.5
Mode 100: jump
Figure 11. Jump timing diagram
EVENTS bus STOP event regs swap
TIME
transmission with subaddr. bit 7 = 1
wait T1ms
wait for Tplllock
wait T0.5ms
wait 50 us
AFSAMPLE
AFHOLD
B.E. OPERATION
mute audio
hold
unmute audio
AC00048
This mode is used to jump to a different frequency and stay there, with reception at the end of the sequence. AFHOLD can be used to tell the back-end to mute/unmute the audio and keep normal processing on hold. AFSAMPLE can be used to tell the back-end when the quality signal processing can be restarted, with a stable situation to start from.
5.2
Mode 100: check
Figure 12. Check timing diagram
EVENTS bus STOP event regs swap
TIME
transmission with subaddr. bit 7 = 1
wait T1ms
wait for Tplllock
AFSAMPLE
AFHOLD
B.E. OPERATION
mute audio
hold
AC00049
This mode is used to jump to a different frequency and stay there, with audio muted. AFHOLD can be used to tell the back-end to mute/unmute the audio and keep normal processing on hold. AFSAMPLE can be used to tell the back-end when to freeze the quality signal processing.
31/60
Tuning state machine
TDA7529
5.3
Mode 110: load
Figure 13. Load timing diagram
EVENTS bus STOP event
TIME
transmission with subaddr. bit 7 = 1
regs swap
AC00050
The content of the buffer and control registers is swapped. No transition occurs on the AFHOLD and AFSAMPLE lines.
5.4
Mode 111: end
Figure 14. End timing diagram
EVENTS bus STOP event
TIME
transmission with subaddr. bit 7 = 1
wait 50 us
AFSAMPLE
AFHOLD
B.E. OPERATION
unmute audio
AC00051
This mode is used to end sequences that terminate with muted audio, after the decision on whether to stay to that frequency or jump to a different one has been taken. AFHOLD can be used to tell the back-end to unmute the audio. AFSAMPLE can be used to tell the back-end to restore normal quality signal processing. Most of the wait times of the algorithm can actually be programmed. The following table summarizes the minimum, maximum and default values of the programmable wait times. The indicated values are valid only for the advised configuration where the phase detector reference frequency is 100 kHz.
32/60
TDA7529 Table 25. Values of the programmable wait times
REGISTER min. Tplllock Byte 15 bits<7:3> default maximum min. T0.5ms Byte 30 bits<7:2> default maximum min. T1ms Byte 20 bits<7:2> default maximum min. T2ms Byte 29 bits<7:2> default maximum min. T60ms Byte 04 bits<7:3> default maximum
Tuning state machine
PARAMETER NAME
VALUE 00000 00110 11111 000000 000101 111111 000000 001100 111111 000000 011000 111111 00000 10111 11111
TIME 20 us 1 ms 5 ms 70 us 0.5 ms 5 ms 10 us 1 ms 5 ms 50 us 2 ms 5 ms 1 ms 60 ms 80 ms
5.5
Register SWAP
Some of these modes contain one or two register "swap" operation(s). The changes within the register structure during a swap operation depend on the operating mode of the chip. If the chip is programmed in the "buffer/control" mode (chosen by setting byte 12 bit 7 = 1), which is necessary to take advantage of the tuning state machine, it is suggested that the microprocessor write data only in the normal register bank (bytes from 16 to 31), because the state machine itself takes care of exchanging the content of the normal register bank with that of the shadow bank (bytes from 32 to 47) during a swap. The normal registers are intended to be written to by the radio microprocessor, whereas the registers that actually control the device circuits are the shadow ones. In any case it is suggested that the bits 5 and 4 of byte 0, that define which control bank is actually used to drive the device circuits, should not be touched after setting them to 0 after reset because they are automatically updated by the tuning state machine.
33/60
Tuning state machine
TDA7529
5.6
State machine start
The tuning state machine is activated only at the end of the transmission if bit 7 of the subaddress is 1. The activation sequence, therefore, is to be done in the following way. Figure 15. Buffer/control serial bus sequence
START ADDRESS (if I2C) SUBADDRESS REGS 0:31 STOP
bit 7 = 1
REG 12 bit 6:4 sets desired state machine mode
sets F2 into buffer registers tuning state machine starts
AC00052
34/60
TDA7529
Registers description
6
Registers description
Figure 16. Registers description
No name r/w
r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
MSB (7)
x ADCclk GPO8_AMAGCv IFin1_AM_FM WAIT60ms(4) divr7 IFAGC_FM_AM FMthr3 AMAGCfat IFAMP_Ictrl2 IMRph3 DZ4 FUNC POL IFAGCin4ctrl WAIT LOCK(4) IFAGCtcAM AMthr3 GPO8hl IFin0_Std_IBOC WAIT1ms(5) divnA20 divnA12 divnA4 VCO1r CPAh3 DAC1A8 DAC2A8 IQselA WAIT2ms(5) WAIT0.5ms(5) IF test
6
x ADCs2 GPO7_FMAGCv KeyAGCen WAIT60ms(3) divr6 IFAGCthr2 FMthr2 AFH_MUX IFAMP_Ictrl1 IMRph2 DZ3 MODE2 PFD_D1 EnSMOOTH WAIT LOCK(3) IFAGCtcFM AMthr2 GPO7hl IFAmpgainA2 WAIT1ms(4) divnA19 divnA11 divnA3 divVA6 CPAh2 DAC1A6 DAC2A6 VCOsw WAIT2ms(4) WAIT0.5ms(4)
5
ShAGC ADCs1 GPIO6_MISO FMAGCpwr WAIT60ms(2) divr5 IFAGCthr1 FMthr1 Vthr5 IredH IMRph1 DZ2 MODE1 PFD_D0 reg48sel WAIT LOCK(2) AMtc1 AMthr1 GPIO6hl IFAmpgainA1 WAIT1ms(3) divnA18 divnA10 divnA2 divVA5 CPAh1 DAC1A5 DAC2A5 WAIT2ms(3) WAIT0.5ms(3)
4
ShPLL ADCs0 GPIO5_Aout AMAGCpwr WAIT60ms(1) divr4 IFAGCthr0 FMthr0 Vthr4 IredL IMRph0 DZ1 MODE0 PLLT4 IFAMP_Ictrl0 WAIT LOCK(1) AMtc0 AMthr0 GPIO5hl IFAmpgainA0 WAIT1ms(2) divnA17 divnA9 divnA1 divVA4 CPAh0 DAC1A4 DAC2A4 WAIT2ms(2) WAIT0.5ms(2)
3
ADCstart GPO4_AMcas MixinFMAM WAIT60ms(0) divr3 FMAGCmodeC1 Vthr3 Casc_ctrl IMRG3 CPcur_800u DS4 PLLT3 RCfreq_1 WAIT LOCK(0) FMtc3 AMAGCmodeC1 GPO4hl MixinFM WAIT1ms(1) divnA16 divnA8 divnA0 divVA3 CPAl3 DAC1A3 DAC2A3 DAC2A0 WAIT2ms(1) WAIT0.5ms(1)
2
ADCen RCenable CP_curr_switch BalunoutIMP disvcc divr2 FMAGCmodeC0 Vthr2 IMRF2 IMRG2 SWfref DS3 PLLT2 RCfreq_0 DIVVtest FMtc2 AMAGCmodeC0 AMAGCinbuffer WAIT1ms(0) divnA15 divnA7 divVA2 CPAl2 DAC1A2 DAC2A2 DAC1A0 WAIT2ms(0) WAIT0.5ms(0)
1
GPIOen ADCautomode GPIO2io Mixout1 PLLtest divr1 GPIO5 output FMAGCmodeV1 Vthr1 IMRF1 IMRG1 divRen DS2 PLLT1 VCOMag1 VCOext FMtc1 AMAGCmodeV1 GPIO2hl RCtest divnA14 divnA6 divVA1 CPAl1 DAC1A1 DAC2A1 DAC2off AGCtest1
LSB (0)
PWR Temp_pwr GPIO1io Mixout2 AMAGC_Isink divr0 IFsection_pwr FMAGCmodeV0 Vthr0 IMRF0 IMRG0 PLLpwr DS1 PLLT0 VCOMag0 LOCK_bit FMtc0 AMAGCmodeV0 GPIO1hl
Power on default
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
0 Short reg 1 ADCctrl 2 GPIOval 3 AGCmixCtrl 4 Misc1 5 DivR 6 IFAGC_SH 7 FMAGC 8 FM_AM_Vthr 9 MIXalign1 10 MIXalign2 11 PLLctrl 12 PLLctrl2 13 PLLtest 14 Misc2 15 WAIT_LOCK 16 AGCtc_A 17 AMAGC_A 18 GPIOm_A 19 IFCTRL_A 20 21 DivN_A1 22 DivN_A2 23 DivN_A3 24 DivV_A 25 CPcur_A 26 DAC1_A 27 DAC2_A 28 PLL_DAC_A 29 Misc4_A 30 31 32 AGCtc_B 33 AMAGC_B 34 GPIOm_B 35 IFCTRL_B 36 AMFilt_B 37 DivN_B1 38 DivN_B2 39 DivN_B3 40 DivV_B 41 CPcur_B 42 DAC1_B 43 DAC2_B 44 PLL_DAC_B 45 Misc4_B 46 47 48 READ_Status 49 READ_ADC
divnA13 divnA5 divVA0 CPAl0 DAC1A1 DAC2A1 DAC1off MIN16 AGCtest0 ADCDAC0
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
ADC test ADCDAC5 ADCDAC4 ADCDAC3 ADCDAC2 ADCDAC1 this byte is valid on the output if bit SHAGC is set to '1', otherwise byte Nr. 16 is valid on the output all bytes from 33 to 45 are valid on the output if SHPLL is set to '1', otherwise byte 17 to 29 are valid on the output
r r
lock ADCok
GPIO6r ADC5
GPIO5r ADC4
MaskMetal1 ADC3
MaskMetal0 ADC2
MaskSet1 ADC1
MaskSet0 ADC0
00h 00h
35/60
Registers description
TDA7529
6.1
6.1.1
Table 26.
MSB D7 D6
Data byte specification
Short_reg (0)
Short_reg (0)
LSB Function D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 0 1 Global PWR Power down the IC Power on the IC GPIO enable all GPIO in tristate all GPIO enable ADCen 6bit ADC on 6bit ADC off ADCstart No conversion Starts a single AD conversion ShPLL PLL register from 17 to 31 are valid PLL register from 33 to 47 are valid ShAGC AGC TC register 16 is valid AGC TC register 32 is valid Not used Not used
0 1 X X
36/60
TDA7529
Registers description
6.1.2
Table 27.
MSB D7 D6
ADCctrl (1)
ADCctrl (1)
LSB Function D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 X 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 Temperature sensor power Enabled Disabled ADC auto mode automatic restart disable automatic restart enable RC oscillator enable enable disable ADCstart (like bit 0.3) ADC input selection Temp sensor FM AGC AM AGC IF AGC VCO tuning voltage (3/5 * Vtune) GP1 GP2 2/5 * VCC ADC clock selection ADC clock source = RC osc ADC clock source = refdiv output
0 1
37/60
Registers description
TDA7529
6.1.3
Table 28.
MSB D7 D6
GPIO mode (2)
GPIO mode (2)
LSB Function D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GPIO1 input / output Analog input to AD converter digital output GPIO2 input / output Analog input to AD converter Digital output CP Current Switch Automatic switch disabled Automatic switch enabled GPIO4 input / output Analog Input digital output GPIO5 input / output digital input output (analog or digital) GPIO6 input / output digital input (or MISO output in SPI mode) digital output (or MISO output in SPI mode) GPIO7 input / output FM AGC voltage output Digital output GPIO8 input / output AM AGC voltage output Digital output
0 1
38/60
TDA7529
Registers description
6.1.4
Table 29.
MSB D7 D6
AGC and mixer control (3)
AGC and mixer control (3
LSB Function D5 D4 D3 D2 D1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 D0 0 1 0 1 Mixout 1 / 2 All Off = power down mixer section Mixout 1 active Mixout 2 active Forbidden state Balun output drive capability Low drive capability High drive capability Mixer input FM / AM selection AM input active FM input active AM AGC On / Off Off On FM AGC On / Off Off On Keyed AGC enable Keyed AGC off keyed AGC on IF input selection FM / AM IF input AM IF input FM
0 1
39/60
Registers description
TDA7529
6.1.5
Table 30.
MSB D7 D6
Register (4)
Register (4)
LSB Function D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 AMAGC Isink (2mA fixed current) Off On PLLtest Off On Disvcc POR activated from IFVCC POR non activated from IFVCC WAIT60ms 1ms (min. value) 60ms (default value) 80ms (max value)
0 1 1
0 0 1
0 1 1
0 1 1
0 1 1
6.1.6
Table 31.
MSB D7 D6
Divider R (5)
Divider R (5)
LSB Divider R value D5 D4 D3 D2 D1 D0 X Divider R value DivR0 : : DivR7
X
40/60
TDA7529
Registers description
6.1.7
Table 32.
MSB D7 D6
IF AGC control (6)
IF AGC control (6)
LSB Function D5 D4 D3 D2 D1 D0 0 1 0 1 X 0 0 : : 1 0 0 : : 1 0 1 : : 1 X IF section On / Off Off On GPIO 5 output mode Off On = GPIO 5 analog output enable Not used IF AGC threshold IF output level = 89dBV(AM) / 91dBV (FM) IF output level = 90.5dBV(AM) / 92.5dBV (FM) : : IF output level = 99dBV(AM) / 101dBV (FM) IF AGC mode FM / AM selection FM mode AM mode
0 1
41/60
Registers description
TDA7529
6.1.8
Table 33.
MSB D7 D6
FM AGC (7)
FM AGC (7)
LSB Function D5 D4 D3 D2 D1 0 0 1 1 0 0 1 1 0 1 0 1 D0 0 1 0 1 Voltage output mode Off N/A Calibration mode Voltage output On Current output mode Off Constant 2mA output Positive current output Neg. / Pos. current output FM AGC threshold Mixer input level = 93dBV (FM1) / 97dBV (FM2) Mixer input level = 94dBV (FM1) / 98dBV (FM2) Mixer input level = 95dBV (FM1) / 99dBV (FM2) Mixer input level = 96dBV (FM1) / 100dBV (FM2) Mixer input level = 97dBV (FM1) / 101dBV (FM2) Mixer input level = 98dBV (FM1) / 102dBV (FM2) Mixer input level = 99dBV (FM1) / 103dBV (FM2) Mixer input level = 100dBV (FM1) / 104dBV (FM2) Mixer input level = 93dBV (FM1) / 97dBV (FM2) Mixer input level = 92dBV (FM1) / 96dBV (FM2) Mixer input level = 91dBV (FM1) / 95dBV (FM2) Mixer input level = 90dBV (FM1) / 94dBV (FM2) Mixer input level = 89dBV (FM1) / 93dBV (FM2) Mixer input level = 88dBV (FM1) / 92dBV (FM2) Mixer input level = 87dBV (FM1) / 91dBV (FM2) Mixer input level = 86dBV (FM1) / 90dBV (FM2)
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
42/60
TDA7529
Registers description
6.1.9
Table 34.
MSB D7 D6
AGC voltage threshold (8)
AGC voltage threshold (8)
LSB Function D5 0 0 : : 1 1 D4 0 0 : : 1 1 D3 0 0 : : 1 1 D2 0 0 : : 1 1 D1 0 0 : : 1 1 D0 Transfer voltage from voltage out to current out 200mV 237.5mV : : 2.5625V 2.6V AM fast attack Off On
0 1 : : 0 1
0 1
6.1.10
Table 35.
MSB D7 D6
Mixer alignment 1 (9)
Mixer alignment 1 (9)
LSB Function D5 D4 D3 D2 0 0 : 1 : 1 0 1 0 0 1 1 0 1 0 1 D1 0 0 : 0 : 1 D0 0 1 : 0 : 1 IQ-filter frequency adjust +2.4MHz +1.8MHz : 0 : -1.8MHz Cascode control loop On / Off On Off Mixers current control Normal bias Low reduction High reduction N/A IFAMP driving capability Normal Intermediate 1 Intermediate 2 High
0 0 1 1
0 1 0 1
43/60
Registers description
TDA7529
6.1.11
Table 36.
MSB D7 D6
Mixer alignment 2 (10)
Mixer alignment 2 (10)
LSB Function D5 D4 D3 0 0 0 : 0 1 : 1 1 D2 1 1 1 : 0 0 : 1 1 D1 1 1 0 : 0 0 : 1 1 D0 1 0 1 : 0 0 : 0 1 IQ-filter gain adjust -0.7dB -0.6dB -0.5dB : 0dB 0dB : +0.6dB +0.7dB IQ-filter phase adjust 0 +0.2 deg +0.2 deg +0.4 deg +0.6 deg : +1.2 deg -1.2 deg -1.0 deg -1.0 deg -0.8 deg -0.6 deg : -0.2 deg 0
0 0 0 0 0 : 0 1 1 1 1 1 : 1 1
0 0 0 0 1 : 1 0 0 0 0 1 : 1 1
0 0 1 1 0 : 1 0 0 1 1 0 : 1 1
0 1 0 1 0 : 1 0 1 0 1 0 : 0 1
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TDA7529
Registers description
6.1.12
Table 37.
MSB D7 D6
PLL control 1 (11)
PLL control 1 (11)
LSB Function D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 PLL enable PLL Off PLL On Divider R enable Divider R off; = div / 1 Divider R on Select reference input Reference frequency input = LVDS Reference frequency input = Xtal Charge pump current 800A 0 A 800 A Slope of high current CP highest : lowest
0 : 1
0 : 1
0 : 1
0 : 1
6.1.13
Table 38.
MSB D7 D6
PLL control 2 (12)
PLL control 2 (12)
LSB Function D5 D4 D3 0 : 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D2 0 : 1 D1 0 : 1 D0 0 : 1 Delay of high current CP shortest : longest State machine modes decode Buffer mode Preset Search AF update Jump Check Load End Register functionality control Normal/shadow mode Buffer/control mode
0 1
45/60
Registers description
TDA7529
6.1.14
Table 39.
MSB D7 D6
PLL test (13)
PLL test (13)
LSB Function D5 D4 X 0 1 D3 X D2 1 D1 0 D0 PLL test Set to default PFD default PFD polarity
0
6.1.15
Table 40.
MSB D7 D6
Misc 2 (14)
Misc 2 (14)
LSB Function D5 D4 D3 D2 D1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 D0 0 1 0 1 VCO magnitude 1V 2V 3V 4V Oscillation frequency of RC oscillator 0.68 MHz 1.31 MHz 1.92 MHz 2.49 MHz IFAMP current control Normal bias High current mode bias Reg48sel ShAGC and ShPLL on D48<1:0> MaskMetal and MaskSet on D48<1:0> EnSMOOTH Smooth disabled Smooth enabled IFAGC control when IN4 selected Normal Thresholds shift
0 1
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TDA7529
Registers description
6.1.16
Table 41.
MSB D7 D6
WAIT LOCK (15)
WAIT LOCK (15)
LSB Function D5 D4 D3 D2 D1 0 0 1 1 D0 0 1 0 1 TEST D18<0> LOCK_bit CMPout VdivOUT WAIT LOCK 0.04ms (min. value) 1ms (default value) 5.08ms (default value)
0 0 1
0 0 1
0 1 1
0 1 1
0 0 1
6.1.17
Table 42.
MSB D7 D6
AGC time constant settings (16 / 32)
AGC time constant settings (16 / 32)
LSB Function D5 D4 D3 D2 D1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 1 0 D0 0 1 0 FM AGC decay time constant D1 D2 D3 FM AGC attack time constant A1 A2 A3 AM AGC time constant T1 T2 T3 IF AGC time constant FM U1 U2 IF AGC time constant AM S1 S2
0 1
47/60
Registers description
TDA7529
6.1.18
Table 43.
MSB D7 D6
AMAGC control (17 / 33)
AMAGC control (17 / 33
LSB Function D5 D4 D3 D2 D1 0 0 1 1 0 0 1 1 0 1 0 1 D0 0 1 0 1 AM AGC voltage output mode Off Voltage output / sense internal Calibration Voltage output / sense external AM AGC current output mode Off Constant 2mA Positive current N/A AM AGC thresholds Mixer input level = 94 dBV Mixer input level = 95 dBV Mixer input level = 96 dBV Mixer input level = 97 dBV Mixer input level = 98 dBV Mixer input level = 99 dBV Mixer input level = 100 dBV Mixer input level = 101 dBV Mixer input level = 94 dBV Mixer input level = 93 dBV Mixer input level = 92 dBV Mixer input level = 91 dBV Mixer input level = 90 dBV Mixer input level = 89 dBV Mixer input level = 88 dBV Mixer input level = 87 dBV
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
48/60
TDA7529
Registers description
6.1.19
Table 44.
MSB D7 D6
GPIO output level control (18 / 34)
GPIO output level control (18 / 34)
LSB Function D5 D4 D3 D2 D1 D0 0 1 0 1 : X : : X : : X : : X : : X : GPIOx high / low output level GPIO1 low GPIO1 high GPIO2 low GPIO2 high : GPIOx low / high : GPIO8 low GPIO8 high
0 1
6.1.20
Table 45.
MSB D7 D6
IF control (19 / 35)
IF control (19 / 35)
LSB Function D5 D4 D3 D2 D1 D0 X 0 1 0 1 0 1 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1 Not used RC test Test enabled Test disabled AMAGC input buffer Buffer enabled Buffer disabled Mixer input selection for FM FM1 mixer input FM2 mixer input IF amplifier Gain 25dB (input1-3) / 19dB (input4) 27dB (input1-3) / 21dB (input4) : 37dB (input1-3) / 31dB (input4) 39dB (input1-3) / 33dB (input4) IF input selection analog / IBOC IBOC Analog
0 1
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Registers description
TDA7529
6.1.21
Table 46.
MSB D7 D6
AF state machine wait time 1 (20 / 36)
AF state machine wait time 1 (20 / 36)
LSB Function D5 D4 D3 D2 D1 D0 X X Not used Not used WAIT 1ms 0.04ms (min. value) 1ms (default value)
0 0
0 0
0 1
0 1
0 0
0 0
6.1.22
Table 47.
MSB D7 D6
PLL main divider (N-divider) 1 (21 / 37)
PLL main divider (N-divider) 1 (21 / 37)
LSB Function D5 D4 D3 D2 D1 D0 X X X X X X X Divider N value M8 M9 M10 M11 M12 M13 M14 M15
X
6.1.23
Table 48.
MSB D7 D6
PLL main divider (N-divider) 2 (22 / 38)
PLL main divider (N-divider) 2 (22 / 38)
LSB Function D5 D4 D3 D2 D1 D0 X X X X X X X Divider N value M0 M1 M2 M3 M4 M5 M6 M7
X
50/60
TDA7529
Registers description
6.1.24
Table 49.
MSB D7 D6
PLL main divider (N-divider) 3 (23 / 39)
PLL main divider (N-divider) 3 (23 / 39)
LSB Function D5 D4 D3 X X X X D2 D1 D0 Divider N value A0 A1 A2 A3 A4
X
6.1.25
Table 50.
PLL Divider ratio calculation
PLL Divider ratio calculation
M counter A counter N= 32*P + A N= M*P + A (P=32) Notes M=32 M>32
M16 M15
...
M7
...
M1
M0
A4
A3
A2
A1
A0
6.1.26
Table 51.
MSB D7 D6
VCO divider (V-divider) (24 / 40)
VCO divider (V-divider) (24 / 40)
LSB Function D5 D4 D3 D2 D1 D0 X X X X X X X Divider V value V0 V1 V2 V3 V4 V5 V6 VCO range selection Range 2 Range 1
0 1
51/60
Registers description
TDA7529
6.1.27
Table 52.
MSB D7 D6
Charge pump current (25 / 41)
Charge pump current (25 / 41)
LSB Function D5 D4 D3 D2 D1 D0 X X X X X X X Low current charge pump 50 A 100 A 200 A 400 A High current charge pump 0.5 mA 1mA 2mA 4mA
X
6.1.28
Table 53.
MSB D7 D6
Tuning DAC 1 (26 / 42)
Tuning DAC 1 (26 / 42)
LSB Function D5 D4 D3 D2 D1 D0 X X X X X X X DAC 1 voltage 8..1 DAC1_. DAC1_2 DAC1_3 DAC1_4 DAC1_5 DAC1_6 DAC1_7 DAC1_8
X
52/60
TDA7529
Registers description
6.1.29
Table 54.
MSB D7 D6
Tuning DAC 2 (27 / 43)
Tuning DAC 2 (27 / 43)
LSB Function D5 D4 D3 D2 D1 D0 X X X X X X X DAC 2 voltage 8..1 DAC2_1 DAC2_2 DAC2_3 DAC2_4 DAC2_5 DAC2_6 DAC2_7 DAC2_8
X
6.1.30 6.1.31
Table 55.
MSB D7 D6
DAC output voltage = 600mV + DACval * 9mV Different controls (28 / 44)
Different controls (28 / 44)
LSB Function D5 D4 D3 D2 D1 D0 0 1 0 1 X X X X X DAC 1 On / Off Off On DAC 2 On / Off Off On DAC 1_0 DAC 2_0 Not used Not used IQ phase select I anticipates Q Q anticipates I
0 1
53/60
Registers description
TDA7529
6.1.32
Table 56.
MSB D7 D6
Misc 3 (29 / 45)
Misc 3 (29 / 45)
LSB Function D5 D4 D3 D2 D1 D0 X X PLL N divider MSB M16 Not used WAIT 2ms 0.08ms (min. value) 2ms (default value) 5.04ms (default value)
0 0 1
0 1 1
0 1 1
0 0 1
0 0 1
0 1 1
6.1.33
Table 57.
MSB D7 D6
Analog test select (30 / 46)
Analog test select (30 / 46)
LSB Function D5 D4 D3 D2 D1 0 0 1 1 D0 0 1 0 1 Analog test output signal select IF AGC FM AGC AMAGC DAC voltage of ADC WAIT 0.5ms 0.02ms (min. value) 0.5ms (default value) 5.06ms (max value)
0 0 1
0 0 1
0 0 1
0 1 1
0 1 1
0 0 1
54/60
TDA7529
Registers description
6.1.34
Table 58.
MSB D7 D6
AD converter test (31 / 47)
AD converter test (31 / 47)
LSB Function D5 D4 D3 D2 D1 D0 X X X X X X 0 1 ADC DAC direct programming DAC 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 ADC test enable Off On AGC test enable Off On
0 1
6.1.35
Table 59.
MSB D7 D6
Read 1 (48)
Read 1 (48)
LSB Function D5 D4 D3 D2 D1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D0 0 1 0 1 Mask set revision A B C D Metal mask revision A B C D GPIO 5 level low high GPIO 6 level low high
55/60
Registers description
TDA7529
6.1.36
Table 60.
MSB D7 D6
Read 2 (49)
Read 2 (49)
LSB Function D5 D4 D3 D2 D1 D0 X X X X X X 0 1 AD converter result ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 AD converter result status Not OK OK
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7
TDA7529
J1
FMANT AMANT XT1 SFEL10M7 muRata
RF
VRF_5V L20
BALUN
VPLL_5V VCC_5V C1
IF
BALUN
VCO
VCC_5V C6666 22uF BLMM18BD102SN1 muRata
DAC1/DAC2 R1 330
BALUN
L1 100nF C69 22uF
IF
C76
VCC_5V IFOUT1 IFOUT2 C4 100nF 1 1uF 1uF
IF
22uF 100nF
PLL
IF
MISO SDA SCL CSN C7 C8 GP5 LLQ2012-FR33 Toko 330 nH L2 100nF 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 C11 GP5 IFin1 IFin2 IFin3 IFin4 TCFM IFdec TCAM BIASD1 VCCIF TCIF2 C10 100nF 1 BALUN1 C14 47 46 45 44 43 42 41 MOSI CLK CS/AS PS GNDBUS VCCRO XTALO XTALI 40 39 38 37 36 35 34 33 REFN C71 REFP 22uF 100nF C33 R5 R6 R8 220 220 22k
BUS
BUS
BLMM18BD102SN1 muRata
2
C5
C6
22nF
GP2/Key
RO
C9
C12
10nF IFOUT1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 680pF 49
IF
REFN REFP IFAGC1 IFAGC2 AFHOLD AFSAMPLE C15 10nF
IFOUT2
CON29 C13 100nF GNDIF 2.2uF TCIF1 IFout1 IFout2 BIASD2 VDDdec VCCBUS MISO/GP6 48 2 Balundec DAC2 DAC1 FMMIX1in FMMIX1dec FMAGC2/GP7 FMAGC1 FMMIX2in FMMIX2dec GNDRF1 AMAGC1 AMMIXdec AMMIXin MIXbiasdec IFAGC1
BALUN
VCCRF2
GP2/Key
GNDRF2
BALUNout2
BALUNout1
C17
100nF
DAC1/DAC2 4 C20 12pF 6 3
RF
Figure 17. Application schematic
3
C21
C18
100nF
C16 39pF C22 680pF FMAGC2/GP7 7 8 9 10 C27 11
RF
C23 22uF
IF
Application schematic
5
R2 C25 SDA SCL 22uF
BUS
100
22uF VDIG_5V
FMANT
R3 220
C19
100nF
R4 1.5k
U1 TDA7529
RF
2
C32 3 10nF 12 13 14 15 C37 100nF 100nF
RF RF
R7 68K
C26 C29
RF
C36 100nF
18pF 1 2
1nF
D2 KP2311E Toko 2
1nF
C24 8.2pF
D1 KP2311E Toko
RF
RF
L3 C28 L6 xxx
RF
1
1
C30 D3 KV1770R Toko C35 16 Toko E558HN-100101 93 nH IFAGC2 GP4/VDS AFHOLD VCCRF1 VCOdec1 Vtune
5.6pF
VDIG_5V L4 BLMM18BD102SN1 muRata
L5
LLQ2012-FR39 Toko 390 nH
C34 22pF
AMAGC2/GP8
AFSAMPLE
VCOdec2
VCOgnd
LFLC
LFHC
GndPLL
VCCPLL
GP1
180nH Toko LLQ2012-FR18
GndRO
RF
RO
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VCO PLL
R9 VRF_5V R11 C39 C40 2k 22uF 100nF 390
RF RF
27 IFAGC2
32
RO
IFAGC1
GP1 C38 100nF C42 10nF R12
4 VPLL_5V C70 22uF L8 BLM18D102SNI muRata
R10 1mH
L7
L9 68uH muRata LQ2MCN680K02B 68uH muRata LQ2MCN680K02B Q1 HN3G01J Thoshiba 1 L10 5 4 2 C44 C47 220nF 3 33pF L11 L12 68pF C45
C48 220pF
4.7K
PLL
AMANT
AFHOLD
AFSAMPLE
R13
10k
C43
22nF
R14 100 VRF_5V
C46
R15
220
4.7nF R16 1M
C49 1uF C52 100nF
VCO
C53 100nF
1
3
C50
C51
2
100nF
2.2uF
AC00053
D4 BAR14-I Infineon LLQ2012-FR33 Toko 330 nH 10uH muRata LQM18FN100M00B
RF
Application schematic
57/60
Package information
TDA7529
8
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 18. LQFP64 (10x10x1.4mm) exposed pad down mechanical data and package dimensions (exposed pad size for D2 and E2: 4.5mm max.)
mm DIM. MIN. A1 A2 b c D D1 D2 D3 E E1 E2 E3 e L L1 k ccc 0.450 0.050 1.350 0.170 0.090 1.400 0.220 TYP. MAX. MIN. TYP. MAX. 0.0059 0.150 0.0020 inch
OUTLINE AND MECHANICAL DATA
1.450 0.0531 0.0551 0.0571 0.270 0.0067 0.0087 0.0106 0.200 0.0035 0.0079
11.800 12.000 12.200 0.4646 0.4724 0.4803 9.800 10.000 10.200 0.3858 0.3937 0.4016 According to Pad size 7.500 0.2953
11.800 12.000 12.200 0.4646 0.4724 0.4803 9.800 10.000 10.200 0.3858 0.3937 0.4016 According to Pad size 7.500 0.500 0.600 1.000 3.500 7.000 0.080 0.2953 0.0197 0.750 0.0177 0.0236 0.0295 0.0394 0.1378 0.2756 0.0031
LQFP64 (10x10x1.4mm) Exposed Pad Down
Note: 1. Exact shape of each corner is optional.
7278841 C
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TDA7529
Revision history
9
Revision history
Table 61.
Date 7-Mar-2007
Document revision history
Revision 1 Initial release. Changes
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TDA7529
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